Using efficient finite field multipliers becomes vital in elliptic curve cryptography (ECC), where data security and authentication are critical. These multipliers do affect performance, however, because they use quite a lot of hardware resources. The Karatsuba algorithm and its variations are explored in this study as a means to enhance hardware efficiency on FPGA devices. Although performance is improved with the overlap-free Karatsuba algorithm. Problems with recombining intermediate findings cause them to add 20% mistakes. We present a modified Karatsuba method that can compute four key outputs for 2-bit inputs error-free to solve this problem. The revised design tested on Artix-7 FPGA and implemented in Verilog HDL, cuts power consumption by 73.95% and area utilization by 95% when compared to the original Karatsuba algorithm. Its overall efficiency is much improved while accuracy is guaranteed, despite a 3.22% increase in area and an 11.12% increase in power compared to the overlap-free version.