Efficient MAC Architecture Using Different Parallel Adders

Mr.A.Prasad; Mrs.N.Swarupa Rani; Batchu Bala Bhargavi; Chinni Yamini; Chityala Lakshmi Devi; Chilakala Anjali

Efficient MAC Architecture Using Different Parallel Adders

Author : Mr.A.Prasad, Mrs.N.Swarupa Rani, Batchu Bala Bhargavi, Chinni Yamini, Chityala Lakshmi Devi, Chilakala Anjali Journa Name: International Journal of Scientific Research & Engineering Trends Volume: 12 issue: 3 Year: Volume-12-issue-3 Views : 21

Abstract:

Because of its capability to do arithmetic operations at fast speeds, the Multiply-Accumulate (MAC) Unit is an essential part of all digital signal processor applications. An 8-bit MAC Unit that can do addition and multiplication is the target of this study. While the MAC Unit uses the same multiplier, it incorporates other adders, including the Kogge-Stone, Ladner-Fischer, Carry Look-Ahead, and Ripple Carry adders. Xilinx ISE was used to implement the structures that were created in Verilog Hardware Description Language (HDL), and ModelSim was used for simulation.